1. Field of the Invention
This invention relates in general to semiconductor memory devices and, more specifically, to latched sense amplifiers in such memory devices having pre-charge circuitry and tri-state outputs.
2. State of the Art
As shown in FIG. 1, in general, a conventional sense amplifier 10 known from Seki, et al., "A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier," IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, pp. 478-483 (1993), receives logic bits output from memory cells (not shown) on complementary bitline bus conductors LD1 and LD2, amplifies the received logic bits at latch output nodes NODE 1 and NODE 2, and outputs the amplified logic bits onto internal data bus conductors (not shown). Output buffers (not shown) connected to the internal data bus conductors then output the logic bits for use by external circuitry (not shown), such as a microprocessor.
More specifically, the sense amplifier 10 begins an operation cycle when an equalization signal SP goes high and turns on equalization NMOS transistors 12 and 14, thereby equalizing electric charge stored on latch output nodes NODE 1 and NODE 2 and on internal nodes NODE 3 and NODE 4. Shortly thereafter, a sense amplifier enabling signal SAC goes high and turns on a current source NMOS transistor 16, thus enabling latching circuitry 18 of the sense amplifier 10. At the same time, the equalized stored charge on latch output nodes NODE 1 and NODE 2 induces a voltage on these nodes of approximately half the supply voltage V.sub.CC (i.e., V.sub.CC /2), which is of sufficient magnitude to moderately turn on sourcing NMOS transistors 20 and 22.
With the latching circuitry 18 enabled, the equalization signal SP goes low to turn off the equalization NMOS transistors 12 and 14. In this state of the sense amplifier 10, the latch output nodes NODE 1 and NODE 2 are isolated from one another, allowing the sense amplifier 10 to latch in a logic bit from the bitline bus conductors LD1 and LD2 when it appears.
A logic bit from a memory cell (not shown) appears in a complementary fashion on the bitline bus conductors LD1 and LD2, with one of the conductors LD1 and LD2 having a voltage of approximately half the supply voltage V.sub.CC (i.e., V.sub.CC /2), and the other having the same voltage less about 200 millivolts (mV) (i.e., (V.sub.CC /2)-200 mV). Thus, a logic "1" bit appears as an approximately 200 mV difference in voltages on the bitline bus conductors LD1 and LD2, with the bitline bus conductor LD1 having the higher voltage. Similarly, a logic "0" bit also appears as an approximately 200 mV difference in voltages on the bitline bus conductors LD1 and LD2, but with the bitline bus conductor LD2 having the higher voltage.
When a logic "1" bit, for example, appears on the bitline bus conductors LD1 and LD2 for latching into the sense amplifier 10, the voltages on the bitline bus conductors LD1 and LD2 representing the logic "1" bit turn on driving transistors 24 and 26, with the higher voltage on the bitline bus conductor LD1 turning on the driving transistor 24 more than the lower voltage on the bitline bus conductor LD2 turns on the driving transistor 26. Because the driving transistor 24 is on more than the driving transistor 26, the charge stored on the latch output node NODE 1 drains to ground through the transistors 24, 20, and 16 more rapidly than the charge stored on the latch output node NODE 2 can drain to ground through the transistors 26, 22, and 16. As a result, the voltage on the latch output node NODE 1 drops more rapidly than the voltage on the latch output node NODE 2.
This more-rapidly-dropping voltage on the latch output node NODE 1 causes a PMOS load transistor 28 and a sourcing PMOS transistor 30 to turn on, thereby pulling the latch output node NODE 2 substantially to the supply voltage V.sub.CC. The supply voltage V.sub.CC on the latch output node NODE 2 then turns the sourcing NMOS transistor 20 fully on, and causes a PMOS load transistor 32 and a sourcing PMOS transistor 34 to be off, thereby causing the transistors 24, 20, and 16 to rapidly drain any remaining charge on the latch output node NODE 1 to ground so that the voltage on the latch output node NODE 1 is substantially at ground. In turn, the ground voltage on the latch output node NODE 1 turns the PMOS load transistor 28 and sourcing PMOS transistor 30 fully on, thereby reinforcing the supply voltage V.sub.CC on the latch output node NODE 2. In this state of the latching circuitry 18, the logic "1" bit is latched in. Of course, if the logic bit is a logic "0" bit, the latching circuitry 18 latches in the logic bit in the opposite manner.
The Seki, et al. sense amplifier 10 of FIG. 1 generally latches in a logic bit more rapidly than many sense amplifiers that preceded it. Still, it is desirable to have a sense amplifier that latches in logic bits even more rapidly to further improve the speed with which the logic bits may be read from semiconductor memory devices.